During semiconductor processing, it is often necessary to reserve a space within a cavity or trench for later processing. For example, during the fabrication of trench-transistor memory cells, a space must be reserved within a partially filled trench for later formation of a wordline. Trench-transistor memory cells are described in more detail in U.S. Pat. No. 4,830,978 by Teng et al., entitled "DRAM Cell and Method," which is incorporated by reference herein.
Typically, a polysilicon spacer is used to reserve space in a partially filled trench. To form the polysilicon spacer, the uppermost portion of the trench is filled with polysilicon, which is subsequently etched to form the spacer. The remaining portion of the trench is filled with a dielectric which surrounds the spacer, and subsequently the polysilicon spacer is removed leaving a void in the trench for the wordline.
This approach has several problems. The polysilicon etched away to form the spacer leaves a residue on the sidewall of the trench. This residue may create an unwanted diffused region on the sidewall during later processing steps. Because etching processes for polysilicon will affect the other materials used in forming the device, namely the dielectric layers formed on the trench sidewalls, the polysilicon is difficult to strip completely without the danger of damaging the dielectric layers. The same problem associated with forming trench-transistors is present in other semiconductor processes which require a spacer to be formed within a cavity.
Therefore, a need has arisen in the industry to provide a method and apparatus for providing a space within a filled cavity which does not leave residue on the sidewalls of the cavity.